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proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released rm5231 rm5231 ? microprocessor with 32-bit system bus data sheet proprietary and confidential issue 1, march 2001
rm5231 ? microprocessor with 32-bit system bus data sheet released proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 2 document id: pmc-2002165, issue 1 legal information copyright ? 2001 pmc-sierra, inc. the information is proprietary and confidential to pmc-sierra, inc., and for its customers? internal use. in any event, you cannot reproduce any part of this document, in any form, without the express written consent of pmc-sierra, inc. pmc-2002165 (r1) disclaimer none of the information contained in this document constitutes an express or implied warranty by pmc- sierra, inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of pmc-sierra, inc., or any portion thereof, referred to in this document. pmc-sierra, inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. in no event will pmc-sierra, inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not pmc-sierra, inc. has been advised of the possibility of such damage. trademarks rm5231 is a trademark of pmc-sierra, inc. contacting pmc-sierra pmc-sierra, inc. 105-8555 baxter place burnaby, bc canada v5a 4v7 tel: (604) 415-6000 fax: (604) 415-6200 document information: document@pmc-sierra.com corporate information: info@pmc-sierra.com technical support: apps@pmc-sierra.com web site: http://www.pmc-sierra.com
rm5231 ? microprocessor with 32-bit system bus data sheet released proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 3 document id: pmc-2002165, issue 1 revision history issue no. issue date ecn number originator details of change 1 march 2001 3287 t. chapman applied pmc-sierra template to existing mpd (qed) framemaker document. revised section 3.14, 3.19, 3.22, 3.25, 3.26, 3.27, 3.30, 3.32, 5, 6, 9.3, 9.4, and the packaging information diagram.
rm5231 ? microprocessor with 32-bit system bus data sheet released proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 4 document id: pmc-2002165, issue 1 document conventions the following conventions are used in this datasheet: all signal, pin, and bus names described in the text, such as extrqst*, are in boldface typeface. all bit and field names described in the text, such as interrupt mask , are in an italic-bold typeface. all instruction names, such as mfhi , are in san serif typeface.
rm5231 ? microprocessor with 32-bit system bus data sheet released proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 5 document id: pmc-2002165, issue 1 table of contents legal information ............................................................................................................. ..............2 revision history .............................................................................................................. ...............3 document conventions .......................................................................................................... .......4 table of contents ............................................................................................................. .............5 list of figures ............................................................................................................... .................7 list of tables ................................................................................................................ .................8 1 features ..................................................................................................................... .............9 2 block diagram ................................................................................................................ .......10 3 hardware overview ............................................................................................................ ...11 3.1 superscalar dispatch ...................................................................................................11 3.2 cpu registers .............................................................................................................1 1 3.3 pipeline ................................................................................................................... .....11 3.4 integer unit ............................................................................................................... ...12 3.5 register file .............................................................................................................. ...12 3.6 alu ........................................................................................................................ ......12 3.7 integer multiply/divide ..................................................................................................12 3.8 floating-point co-processor ........................................................................................13 3.9 floating-point unit .......................................................................................................1 3 3.10 floating-point general register file ............................................................................15 3.11 system control co-processor (cp0) ............................................................................15 3.12 system control co-processor registers .....................................................................15 3.13 virtual to physical address mapping ............................................................................16 3.14 joint tlb ................................................................................................................. .....17 3.15 instruction tlb ........................................................................................................... ..18 3.16 data tlb .................................................................................................................. ....18 3.17 cache memory .............................................................................................................1 8 3.18 instruction cache ......................................................................................................... 18 3.19 data cache ................................................................................................................ ..19 3.20 write buffer .............................................................................................................. ....20 3.21 system interface .......................................................................................................... 21 3.22 system address/data bus ...........................................................................................21 3.23 system command bus ................................................................................................21 3.24 handshake signals ......................................................................................................22 3.25 non-overlapping system interface ...............................................................................22 3.26 enhanced write modes ................................................................................................23 3.27 external requests ........................................................................................................2 4 3.28 interrupt handling ........................................................................................................ 24 3.29 standby mode .............................................................................................................. 24 3.30 jtag interface ............................................................................................................ .24
rm5231 ? microprocessor with 32-bit system bus data sheet released proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 6 document id: pmc-2002165, issue 1 3.31 boot-time options .......................................................................................................24 3.32 boot-time modes .........................................................................................................25 4 pin descriptions ............................................................................................................. .......26 5 absolute maximum ratings ..................................................................................................29 6 recommended operating conditions ...................................................................................30 7 dc electrical characteristics ................................................................................................ .31 8 power consumption ............................................................................................................ ..32 9 ac electrical characteristics ................................................................................................ .33 9.1 capacitive load deration .............................................................................................33 9.2 clock parameters ........................................................................................................33 9.3 system interface parameters .......................................................................................34 9.4 boot-time interface parameters ..................................................................................34 10 timing diagrams ............................................................................................................. ......35 10.1 system interface timing ..............................................................................................35 11 packaging information ....................................................................................................... ...36 12 rm5231 128-pin pqfp package pinout ...............................................................................38 13 ordering information ........................................................................................................ .....39
rm5231 ? microprocessor with 32-bit system bus data sheet released proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 7 document id: pmc-2002165, issue 1 list of figures figure 1 block diagram ...................................................................................................... .......10 figure 2 cpu registers ...................................................................................................... .......11 figure 3 pipeline ........................................................................................................... .............12 figure 4 cp0 registers ...................................................................................................... .......16 figure 5 kernel mode virtual addressing ..................................................................................17 figure 6 typical embedded system block diagram ................................................................21 figure 7 processor block read ............................................................................................... ..23 figure 8 processor block write .............................................................................................. ...23 figure 9 clock timing ....................................................................................................... .........35 figure 10 input timing ...................................................................................................... .........35 figure 11 output timing ..................................................................................................... .......35
rm5231 ? microprocessor with 32-bit system bus data sheet released proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 8 document id: pmc-2002165, issue 1 list of tables table 1 integer multiply/divide operations ................................................................................13 table 2 floating-point instruction cycles ..................................................................................1 4 table 3 cache attributes .................................................................................................... .......20 table 4 boot-time mode bit stream .........................................................................................25 table 5 system interface .................................................................................................... .......26 table 6 clock/control interface ............................................................................................. ....27 table 7 interrupt interface ................................................................................................. ........27 table 8 jtag interface ...................................................................................................... .......27 table 9 initialization interface ............................................................................................ ........28 table 10 power supply ....................................................................................................... ......28
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 9 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released 1 features dual issue superscalar microprocessor ? 150, 200, & 250 mhz operating frequencies 300 dhrystone2.1 mips system interface optimized for embedded applications 32-bit system interface lowers total system cost high-performance write protocols maximize uncached write bandwidth processor clock multipliers: 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9 2.5 v core with 3.3 v ios ieee 1149.1 jtag boundary scan integrated on-chip caches 32 kb instruction and 32 kb data ? 2 way set associative per set locking virtually indexed, physically tagged write-back and write-through on a per page basis pipeline restart on first doubleword for data cache misses integrated memory management unit fully associative joint tlb (shared by i and d translations) 48 dual entries map 96 pages variable page size (4 kb to 16 mb in 4x increments) high-performance floating-point unit ? up to 500 mflops single cycle repeat rate for common single-precision operations and some double pre- cision operations two cycle repeat rate for double-precision multiply and double precision combined multiply-add operations single cycle repeat rate for single-precision combined multiply-add operation mips iv instruction set floating point multiply-add instruction increases performance in signal processing and graphics applications conditional moves to reduce branch frequency index address modes (register + register) embedded application enhancements specialized dsp integer multiply-accumulate instructions and 3-operand multiply instruction i and d cache locking by set optional dedicated exception vector for interrupts fully static 0.25 micron cmos design with power down logic standby reduced power mode with wait instruction 2.5 v core with 3.3 v i/o 128-pin power-quad 4 (qfp) package
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 10 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released 2 block diagram figure 1 block diagram integer address/adder instruction dispatch unit primary data cache 2-way set associative primary instruction cache 2-way set associative dtag dtlb itag itlb fp instruction register integer instruction register store buffer write buffer read buffer pad buffer address buffer load aligner integer register file dtlb virtual pll/clocks floating-point load/align floating-point register file packer/unpacker floating-point multadd, add, sub, cvt, div, sqrt joint tlb coprocessor 0 system/memory control pc incrementer branch pc adder itlb virtual program counter int mult, div, madd floating-point control integer control dva iva pad bus d bus fp bus integer bus fa bus a/d bus shifter/store aligner logic unit
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 11 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released 3 hardware overview the rm5231 offers a high-level of integration targeted at high-performance embedded applications. the key elements of the rm5231 are briefly described in this section. 3.1 superscalar dispatch the rm5231 has an asymmetric superscalar dispatch unit which allows it to issue an integer instruction and a floating-point computation instruction simultaneously. integer instructions include alu, branch, load/store, and floating-point load/store, while floating-point computation instructions include floating-point add, subtract, combined multiply-add, converts, etc. in combination with its high-throughput fully pipelined floating-point execution unit, the superscalar capability of the rm5231 provides unparalleled price/performance in computationally intensive embedded applications. 3.2 cpu registers the rm5231 cpu has a user-visible state consisting of 32 general purpose registers, two special purpose registers for integer multiplication and division, a program counter, and no condition code bits. figure 2 shows the user visible state. figure 2 cpu registers 3.3 pipeline for integer operations, loads, stores, and other non-floating-point operations, the rm5231 uses a 5-stage pipeline. in addition to the integer pipeline, the rm5231 uses an extended 7-stage pipeline for floating-point operations. figure 3 shows the rm5231 integer pipeline. as illustrated in the figure, up to five integer instructions can be executing simultaneously. general purpose registers 63 0 multiply/divide registers 0 63 0 r1 hi r2 63 0 lo program counter 63 0 r29 pc r30 r31
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 12 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released figure 3 pipeline 3.4 integer unit the rm5231 integer unit includes thirty-two general purpose 64-bit registers, a load/store architecture with single cycle alu operations (add, sub, logical, shift) and an autonomous multiply/divide unit. additional register resources include: the hi/lo result registers for the two- operand integer multiply/divide operations, and the program counter (pc). the rm5231 implements the mips iv instruction set architecture, and is therefore fully upward compatible with applications that run on processors implementing the earlier generation mips i- iii instruction sets. 3.5 register file the rm5231 has thirty-two general purpose registers with register location 0 (r0) hard wired to a zero value. these registers are used for scalar integer operations and address calculation. the register file has two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. 3.6 alu the rm5231 alu consists of an integer adder/subtractor, a logic unit, and a shifter. the adder performs address calculations in addition to arithmetic operations. the logic unit performs all logical and zero shift data moves. the shifter performs shifts and store alignment operations. each of these units is optimized to perform all operations in a single processor cycle. 3.7 integer multiply/divide the rm5231 has a dedicated integer multiply/divide unit optimized for high-speed multiply and multiply-accumulate operations. table 1 shows the performance of the multiply/divide unit on each operation. i0 i1 i2 i3 i4 2i 1i 1r 2r 1a 2a 1d 2d 1w 2w 2i 1i 1r 2r 1a 2a 1d 2d 1w 2w 2i 1i 1r 2r 1a 2a 1d 2d 1w 2w 2i 1i 1r 2r 1a 2a 1d 2d 1w 2w 2i 1i 1r 2r 1a 2a 1d 2d 1w 2w one cycle 1i-1r: 2i: 2a-2d: 2r: 1a-2a: 1a: 1a: 1d: 2a: 2w: instruction cache access instruction virtual to physical address translation register file read, bypass calculation, instruction decode, branch address calculation issue or slip decision, branch decision integer add, logical, shift data virtual address calculation data virtual to physical address translation store align register file write data cache access and load align
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 13 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released table 1 integer multiply/divide operations the baseline mips iv isa specifies that the results of a multiply or divide operation be placed in the hi and lo registers. these values can then be transferred to the general purpose register file using the move-from-hi and move-from-lo ( mfhi / mflo ) instructions. in addition to the baseline mips iv integer multiply instructions, the rm5231 also implements the 3 operand multiply instruction, mul . this instruction specifies that the multiply result go directly to the integer register file rather than the lo register. the portion of the multiply that would have normally gone into the hi register is discarded. for applications where it is known that the upper half of the multiply result is not required, using the mul instruction eliminates the necessity of executing an explicit mflo instruction. also included in the rm5231 are the multiply-add instructions, madu / mad . this instruction multiplies two operands and adds the resulting product to the current contents of the hi and lo registers. the multiply-accumulate operation is the core primitive of almost all signal processing algorithms allowing the rm5231 to eliminate the need for a separate dsp engine in many embedded applications. 3.8 floating-point co-processor the rm5231 incorporates a high-performance fully pipelined floating-point co-processor which includes a floating-point register file and autonomous execution units for multiply/add/convert and divide/square root. the floating-point coprocessor is a tightly coupled execution unit, decoding and executing instructions in parallel with, and in the case of floating-point loads and stores, in cooperation with the integer unit. the superscalar capabilities of the rm5231 allow floating-point computation instructions to issue concurrently with integer instructions. 3.9 floating-point unit the rm5231 floating-point execution unit supports single and double precision arithmetic, as specified in the ieee standard 754. the execution unit is broken into a separate divide/square root unit and a pipelined multiply/add unit. overlap of the divide/square root and multiply/add operations is supported. the rm5231 maintains fully precise floating-point exceptions while allowing both overlapped and pipelined operations. precise exceptions are extremely important in object-oriented programming environments and highly desirable for debugging in any environment. opcode operand size latency repeat rate stall cycles mult/u, mad/u 16 bit 3 2 0 32 bit 4 3 0 mul 16 bit 3 2 1 32 bit 4 3 2 dmult, dmultu any 7 6 0 div, divd any 36 36 0 ddiv, ddivu any 68 68 0
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 14 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released floating-point operations includes: add subtract multiply divide square root reciprocal reciprocal square root conditional moves conversion between fixed-point and floating-point format conversion between floating-point formats, and floating-point compare. table 2 gives the latencies of the floating-point instructions in internal processor cycles. table 2 floating-point instruction cycles operation latency repeat rate fadd 4 1 fsub 4 1 fmult 4/5 1/2 fmadd 4/5 1/2 fmsub 4/5 1/2 fdiv 21/36 19/34 fsqrt 21/36 19/34 frecip 21/36 19/34 frsqrt 38/68 36/66 fcvt.s.d 4 1 fcvt.s.w 6 3 fcvt.s.l 6 3 fcvt.d.s 4 1 fcvt.d.w 4 1 fcvt.d.l 4 1 fcvt.w.s 4 1 fcvt.w.d 4 1 fcvt.l.s 4 1 fcvt.l.d 4 1 fcmp 1 1 fmov 1 1 fmovc 1 1 fabs 1 1 fneg 1 1 note: numbers are represented as single/double precision format.
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 15 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released 3.10 floating-point general register file the floating-point general register file (fgr) is made up of thirty-two 64-bit registers. with the floating-point load and store double instructions ( ldc1 and sdc1 ), the floating-point unit can take advantage of the 64-bit wide data cache and issue a floating-point co-processor load or store doubleword instruction in every cycle. the floating-point control register space contains two registers; one for determining configuration and revision information for the coprocessor and one for control and status information. these are primarily used for diagnostic software, exception handling, state saving and restoring, and control of rounding modes. to support superscalar operation, the fgr has four read ports and two write ports, and is fully bypassed to minimize operation latency in the pipeline. three of the read ports and one write port are used to support the combined multiply-add instruction while the fourth read and second write port allows a concurrent floating-point load or store. 3.11 system control co-processor (cp0) the system control co-processor, also called coprocessor 0 or cp0 in the mips architecture, is responsible for the virtual memory sub-system, the exception control system, and the diagnostics capability of the processor. in the mips architecture, the system control co-processor (and thus the kernel software) is implementation dependent. the memory management unit controls the virtual memory system page mapping. it consists of an instruction address translation buffer, itlb, a data address translation buffer, dtlb, a joint instruction and data address translation buffer, jtlb, and co-processor registers used by the virtual memory mapping sub-system. 3.12 system control co-processor registers the rm5231 incorporates all system control co-processor (cp0) registers on-chip. these registers provide the path through which the virtual memory system ? s page mapping is examined and modified, exceptions are handled, and operating modes are controlled (kernel vs. user mode, interrupts enabled or disabled, cache features). in addition, the rm5231 includes registers to implement a real-time cycle counting facility to aid in cache diagnostic testing and to assist in data error detection. figure 4 shows the cp0 registers.
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 16 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released figure 4 cp0 registers 3.13 virtual to physical address mapping the rm5231 provides three modes of virtual addressing: user mode kernel mode supervisor mode this mechanism is available to system software to provide a secure environment for user processes. bits in the cp0 status register determine which virtual addressing mode is used. in the user mode, the rm5231 provides a single, uniform virtual address space of 1tb (2 gb in 32-bit mode). when operating in the kernel mode, four distinct virtual address spaces, totalling over 2.5 tb (4 gb in 32-bit mode), are simultaneously available and are differentiated by the high-order bits of the virtual address. the rm5231 processors also support a supervisor mode in which the virtual address space over 2 tb (2.5 gb in 32-bit mode), divided into three regions based on the high-order bits of the virtual address. when the rm5231 is configured as a 64-bit microprocessor, the virtual address space layout is an upward compatible extension of the 32-bit virtual address space layout. figure 5 shows the address space layout for 32-bit operation. 0 47 tlb (entries protected from tlbwr) entryhi 10* entrylo0 2* entrylo1 3* pagemask 5* wired 6* random 1* index 0* status 12* cause 13* epc 14* errorepc 30* count 9* compare 11* context 4* prid 15* config 16* ta gh i 29* taglo 28* ecc 26* cacheerr 27* badvaddr 8* lladdr 17* * register number xcontext 20* used for memory management used for exception processing
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 17 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released figure 5 kernel mode virtual addressing (32-bit) 3.14 joint tlb for fast virtual-to-physical address translation, the rm5231 uses a large, fully associative tlb that maps 96 virtual pages to their corresponding physical addresses. as indicated by its name, the joint tlb (jtlb) is used for both instruction and data translations. the jtlb is organized as 48 pairs of even-odd entries, and maps a virtual address and address space identifier into the large, 64 gb physical address space. two mechanisms are provided to assist in controlling the amount of mapped space and the replacement characteristics of various memory regions. first, the page size can be configured, on a per-entry basis, to use page sizes in the range of 4 kb to 16 mb (in multiples of 4). the cp0 page mask register is loaded with the desired page size of a mapping, and that size is stored into the tlb along with the virtual address when a new entry is written. thus, operating systems can create special purpose maps; for example, an entire frame buffer can be memory mapped using only one tlb entry. the second mechanism controls the replacement algorithm when a tlb miss occurs. the rm5231 provides a random replacement algorithm to select a tlb entry to be written with a new mapping. however, the processor also provides a mechanism whereby a system specific number of mappings can be locked into the tlb, thereby avoiding random replacement. this mechanism allows the operating system to guarantee that certain pages are always mapped for performance reasons and for deadlock avoidance. this mechanism also facilitates the design of real-time systems by allowing deterministic access to critical software. 0xffffffff kernel virtual address space (kseg3) mapped, 0.5 gb 0xe0000000 0xdfffffff supervisor virtual address space (ksseg) mapped, 0.5 gb 0xc0000000 0xbfffffff uncached kernel physical address space (kseg1) unmapped, 0.5 gb 0xa0000000 0x9fffffff cached kernel physical address space (kseg0) unmapped, 0.5 gb 0x80000000 0x7fffffff user virtual address space (kuseg) mapped, 2.0 gb 0x00000000
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 18 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released the jtlb also contains information that controls the cache coherency protocol for each page. specifically, each page has attribute bits to determine the following coherency algorithms: uncached non-coherent write-back non-coherent write-through with write-allocate non-coherent write-through without write-allocate sharable exclusive update the non-coherent protocols are used for both code and data on the rm5231, with data using write- back or write-through depending on the application. the coherency attributes generate coherent transaction types on the system interface. however, in the rm5231 cache coherency is not supported, hence the coherency attributes should never be used. 3.15 instruction tlb the rm5231 implements a 2-entry instruction tlb (itlb) to minimize contention for the jtlb, eliminate the timing critical path of translating through a large associative array, and save power. each itlb entry maps a 4 kb page. the itlb improves performance by allowing instruction address translation to occur in parallel with data address translation. when a miss occurs on an instruction address translation by the itlb, the least-recently used itlb entry is filled from the jtlb. the operation of the itlb is completely transparent to the user. 3.16 data tlb the rm5231 implements a 4-entry data tlb (dtlb) for the same reasons cited above for the itlb. each dtlb entry maps a 4 kb page. the dtlb improves performance by allowing data address translation to occur in parallel with instruction address translation. when a miss occurs on a data address translation by the dtlb, the dtlb is filled from the jtlb. the dtlb refill is pseudo-lru: the least recently used entry of the least recently used pair of entries is filled. the operation of the dtlb is completely transparent to the user. 3.17 cache memory in order to keep the rm5231 ? s high-performance pipeline full and operating efficiently, the rm5231 incorporates on-chip instruction and data caches that can be accessed in a single processor cycle. each cache has its own 64-bit data path and both caches can be accessed simultaneously. the cache subsystem provides the integer and floating-point units with an aggregate bandwidth of over 3 gb per second at an internal clock frequency of 200 mhz. 3.18 instruction cache the rm5231 incorporates a two-way set associative on-chip instruction cache. this virtually indexed, physically tagged cache is 32 kb in size and is protected with word parity. since the cache is virtually indexed, the virtual-to-physical address translation occurs in parallel with the cache access, further increasing performance by allowing these two operations to occur
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 19 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released simultaneously. the cache tag contains a 24-bit physical address, a valid bit, and has a single parity bit. the instruction cache is 64-bits wide and can be accessed each processor cycle. accessing 64 bits per cycle allows the instruction cache to supply two instructions per cycle to the superscalar dispatch unit. for typical code sequences where a floating-point load or store and a floating-point computation instruction are being issued together in a loop, the entire bandwidth available from the instruction cache will be consumed. cache miss refill writes 64 bits per cycle to minimize the cache miss penalty. the line size is eight instructions (32 bytes) to maximize the performance of communication between the processor and the memory system. the rm5231 supports instruction cache locking. the contents of one set of the cache, set a, can be locked by setting a bit in the coprocessor 0 status register. locking the set prevents its contents from being overwritten by a subsequent cache miss. refill will occur only into set b. this mechanism allows the programmer to lock critical code into the cache thereby guaranteeing deterministic behavior for the locked code sequence. 3.19 data cache for fast, single cycle data access, the rm5231 includes a 32 kb on-chip data cache that is two- way set associative with a fixed 32-byte (eight words) line size. the data cache is protected with byte parity and its tag is protected with a single parity bit. it is virtually indexed and physically tagged to allow simultaneous address translation and data cache access. cache protocols supported for the data cache are: 1. uncached data loads and instruction fetches from uncached memory space are brought in from the main memory to the register file and the execution unit, respectfully. the caches are not accessed. data stores to uncached memory space go directly to the main memory without updating the data cache. 2. write-back loads and instruction fetches first search the cache, reading main memory only if the desired data is not cache resident. on data store operations, the cache is first searched to determine if the target address is cache resident. if it is resident, the cache contents are updated, and the cache line is marked for later write-back. if the cache lookup misses, the target cache line is first brought into the cache and then the write is performed as above. 3. write-through with write allocate loads and instruction fetches first search the cache, reading main memory only if the desired data is not cache resident. on data store operations, the cache is first searched to determine if the target address is cache resident. if it is resident, the cache contents are updated and main memory is written, leaving the write-back bit of the cache line unchanged. if the cache lookup misses, the target line is first brought into the cache and then the write is performed as above.
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 20 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released 4. write-through without write allocate loads and instruction fetches first search the cache, reading main memory only if the desired data is not cache resident. on data store operations, the cache is first searched to determine if the target address is cache resident. if it is resident, the cache contents are updated and main memory is written, leaving the write-back bit of the cache line unchanged. if the cache lookup misses, then only main memory is written. the most commonly used write policy is write-back, where a store to a cache line does not immediately cause the main memory to be updated. this increases system performance by reducing bus traffic and eliminating the bottleneck of waiting for each store operation to finish before issuing a subsequent memory operation. software can, however, select write-through on a per-page basis when appropriate, such as for frame buffers. associated with the data cache is the store buffer. when the rm5231 executes a store instruction, this single-entry buffer gets written with the store data while the tag comparison is performed. if the tag matches, then the data is written into the data cache in the next cycle that the data cache is not accessed (the next non-load cycle). the store buffer allows the rm5231 to execute a store every processor cycle and to perform back-to-back stores without penalty. in the event of a store immediately followed by a load to the same address, a combined merge and cache write occurs such that no penalty is incurred. the rm5231 cache attributes for both the instruction and data caches are summarized in table 3. table 3 cache attributes 3.20 write buffer writes to external memory, whether cache miss write-backs or stores to uncached or write-through addresses, use the on-chip write buffer. the write buffer holds up to four 64-bit address and data pairs. the entire buffer is used for a data cache write-back and allows the processor to proceed in parallel with the memory update. for uncached and write-through stores, the write buffer characteristics instruction data size 32 kb 32 kb organization 2-way set associative 2-way set associative line size 32 b 32 b index vaddr 11..0 vaddr 11..0 tag paddr 31..12 paddr 31..12 write policy n.a. write-back/write- through read order sub-block sub-block write order sequential sequential miss restart after transfer of entire line first double parity per-word per-byte cache locking set a set a
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 21 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released significantly increases performance by decoupling the sysad bus transfers from the instruction execution stream. 3.21 system interface the system interface consists of a 32-bit address/data bus with 4 parity check bits and a 9-bit command bus. in addition, there are 6 handshake signals and 6 interrupt inputs. the interface is capable of transferring data between the processor and memory at a peak rate of 400 mb/sec with a 100 mhz sysclock. figure 6 shows a typical embedded system using the rm5231. in this example, a bank of drams and a memory controller asic share the processor ? s sysad bus while the memory controller provides separate ports to a boot rom and an i/o system. figure 6 typical embedded system block diagram 3.22 system address/data bus the 32-bit system address data ( sysad ) bus is used to transfer addresses and data between the rm5231 and the rest of the system. it is protected with a 4-bit parity check bus ( sysadc ). the system interface is configurable to allow easy interfacing to memory and i/o systems of varying frequencies. the block write data rate, non-block write protocol, and output drive strength are programmable at boot time via the mode control bits. the rate at which the processor receives data is fully controlled by the external device. 3.23 system command bus the rm5231 interface has a 9-bit system command ( syscmd ) bus. the command bus indicates whether the sysad bus carries address or data information on a per-clock basis. if the sysad carries address, then the syscmd bus also indicates what type of transaction is to take place (for example, a read or write). if the sysad carries data, then the syscmd bus also gives information about the data (for example, this is the last data word transmitted, or the data contains an error). the syscmd bus is bidirectional to support both processor requests and external requests to the rm5231. processor requests are initiated by the rm5231 and responded to by an external device. external requests are issued by an external device and require the rm5231 to respond. rm5231 memory i/o controller flash/ control x x 36 boot pci bus rom 36 8 23 latch dram address
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 22 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released the rm5231 supports one- to four-byte transfers as well as block transfers on the sysad bus. in the case of a sub-word transfer, the two low-order address bits give the byte address of the transfer, and the syscmd bus indicates the number of bytes being transferred. 3.24 handshake signals there are six handshake signals on the system interface. two of these, rdrdy* and wrrdy* , are used by an external device to indicate to the rm5231 whether it can accept a new read or write transaction. the rm5231 samples these signals before deasserting the address on read and write requests. extrqst* and release* are used to transfer control of the sysad and syscmd buses from the processor to an external device. when an external device needs to control the interface, it asserts extrqst* . the rm5231 responds by asserting release* to release the system interface to slave state. validout* and validin* are used by the rm5231 and the external device respectively to indicate that there is a valid address, a command, or data on the sysad and syscmd buses. the rm5231 asserts validout* when it is driving these buses with a valid address, a command or data, and the external agent drives validin* when it has control of the system interface and is driving a valid address, a command or data. 3.25 non-overlapping system interface the rm5231 requires a non-overlapping system interface. this means that only one processor request may be outstanding at a time and that the request must be serviced by an external agent before the rm5231 issues another request. the rm5231 can issue read and write requests to an external device, whereas an external device can issue null and write requests to the rm5231. for processor reads the rm5231 asserts validout* and simultaneously drives the address and read command on the sysad and syscmd buses respectively. if the system interface has rdrdy* asserted, then the processor tristates its drivers and releases the system interface to the slave state by asserting release* . the external device can then begin sending data to the rm5231. figure 7 shows a processor block read request and the external agent read response. the read latency is 4 cycles ( validout* to validin* ), and the response data pattern is ? wwwwwwww ? , indicating that data can be transferred on every clock with no wait states in-between.
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 23 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released figure 7 processor block read figure 8 shows a processor block write using write response pattern ? wwwwwwww ? , or code 0, of the boot time mode select options. figure 8 processor block write 3.26 enhanced write modes the rm5231 implements two enhancements to the original r4000 write mechanism: write reissue and pipeline writes. the original r4000 allowed a write address cycle on the sysad bus only once every four sysclock cycles. hence for a non-block write, this meant that two out of every four cycles were wait states. pipelined write mode eliminates these two wait states by allowing the processor to drive a new write address onto the bus immediately after the previous write data cycle. this allows for higher sysad bus utilization. however, at high bus frequencies the processor may drive a subsequent write onto the bus prior to the time the external agent deasserts wrrdy* , indicating that it can not accept another write cycle. this can cause the write cycle to be missed. write reissue mode is an enhancement to pipelined write mode and allows the processor to reissue missed write cycles. if wrrdy* is deasserted during the issue phase of a write operation, the cycle is aborted by the processor and reissued at a later time. sysclock sysad syscmd validout* validin* rdrdy* wrrdy* release* addr data0 data1 data2 data3 data4 data5 data6 data7 read ndata ndata ndata ndata ndata ndata ndata neod sysclock sysad syscmd validout* validin* rdrdy* wrrdy* release* addr data0 data1 data2 data3 data4 data5 data6 data7 write ndata ndata ndata ndata ndata ndata ndata neod
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 24 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released in write reissue mode, a write rate of one write every two bus cycles can be achieved. pipelined writes have the same two bus cycle write repeat rate, but can issue one additional write following the deassertion of wrrdy* . 3.27 external requests the external request pin, extrqst* , is asserted by the external agent when it requires mastership of the system interface, either to perform an independent transfer or to write to the interrupt register within the rm5231. an independent transfer is a data transfer between two external agents or between an external agent and memory or peripheral on the system interface. following the asserting of the extrqst*, the rm5231 tri-states its drivers allowing the external agent to use the system interface buses to complete an independent transfer. the external agent is responsible for returning mastership of the system interface to the rm5231 when it has completed the independent transfer and does so by executing an external null cycle. 3.28 interrupt handling in order to provide better real time interrupt handling, the rm5231 supports a dedicated interrupt vector. when enabled by the real time executive, by setting a bit in the cause register, interrupts vector to a specific address which is not shared with any of the other exception types. this capability eliminates the need to go through the normal software routine for exception decode and dispatch, thereby lowering interrupt latency. 3.29 standby mode the rm5231 provides a means to reduce the amount of power consumed by the internal core when the cpu would otherwise not be performing any useful operations. this state is known as standby mode. executing the wait instruction enables interrupts causes the processor to enter standby mode. when the wait instruction completes the w pipe stage, and if the sysad bus is currently idle, the internal processor clocks stop, thereby freezing the pipeline. the phase lock loop, or pll, internal timer/counter, and the ? wake up ? input pins: int[5:0]* , nmi* , extreq* , reset* , and coldreset* will continue to operate in their normal fashion. if the sysad bus is not idle when the wait instruction completes the w pipe-stage, then the wait is treated as a nop until the bus operation is completed. once the processor is in standby, any interrupt, including the internally generated timer interrupt, will cause the processor to exit standby and resume operation where it left off. the wait instruction is typically inserted in the idle loop of the operating system or real time executive. 3.30 jtag interface the rm5231 interface supports jtag test access port (tap) boundary scan in conformance with the ieee 1149.1 specification. the jtag interface is especially helpful for checking the integrity of the processors pin connections. 3.31 boot-time options fundamental operational modes for the processor are initialized by the boot-time mode control interface. this serial interface operates at a very low frequency (sysclock divided by 256). the
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 25 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released low frequency operation allows the initialization information to be kept in a low cost eprom or a system interface asic. immediately after the vccok signal is asserted, the processor reads a serial bit stream of 256 bits to initialize all the fundamental operational modes. modeclock run continuously from the assertion of vccok . 3.32 boot-time modes the boot-time serial mode stream is defined in table 4. bit 0 is the bit presented to the processor as the first bit in the stream when vccok is asserted. bit 255 is the last bit transferred. table 4 boot-time mode bit stream mode bit description mode bit description 0 reserved: must be zero 14:13 output driver strength - 100% = fastest 00: 67% strength 01: 50% strength 10: 100% strength 11: 83% strength 4:1 write-back data rate (w = write data transfer, x = wait state) 0: wwwwwwww 1: wwxwwxwwxwwx 2: wwxxwwxxwwxxwwxx 3: wxwxwxwxwxwxwxwx 4: wwxxxwwxxxwwxxxwwxxx 5: wwxxxxwwxxxxwwxxxxwwxxxx 6: wxxwxxwxxwxxwxxwxxwxxwxx 7: wwxxxxxxwwxxxxxxwwxxxxxxwwxxxxxx 8: wxxxwxxxwxxxwxxxwxxxwxxxwxxxwxxx 9-15 reserved 15 reserved: must be zero 7:5 pclock to sysclock multiplier mode bits 7:5 mode bit 20=0 mode bit 20=1 000 multiply by 2 n/a 001 multiply by 3 n/a 010 multiply by 4 n/a 011 multiply by 5 multiply by 2.5 100 multiply by 6 n/a 101 multiply by 7 multiply by 3.5 110 multiply by 8 n/a 111 multiply by 9 multiply by 4.5 17:16 system configuration identifiers - software visible in config[21..20] register 8 specifies byte ordering. logically ored with bigendian input signal. 0: little endian 1: big endian 19:18 reserved: must be zero 10:9 non-block write protocol 00: r4000 compatible 01: reserved 10: pipelined 11: write re-issue 20 select sysclock to pclock multiply mode 0: integer multipliers 1: half-integer multipliers 11 timer interrupt enable/disable 0: enable the timer interrupt on int5* 1: disable the timer interrupt on int5* 21 reserved: must be one 12 reserved: must be zero 255:22 reserved: must be zero
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 26 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released 4 pin descriptions the following is a list of interface, interrupt, and miscellaneous pins available on the rm5231. table 5 system interface pin name type description extrqst* input external request signals that the system interface is submitting an external request. release* output release interface signals that the processor is releasing the system interface to slave state. rdrdy* input read ready signals that an external agent can now accept a processor read. wrrdy* input write ready signals that an external agent can now accept a processor write request. validin* input valid input signals that an external agent is now driving a valid address or data on the sysad bus and a valid command or data identifier on the syscmd bus. validout* output valid output signals that the processor is now driving a valid address or data on the sysad bus and a valid command or data identifier on the syscmd bus. sysad[31:0] input/output system address/data bus a 32-bit address and data bus for communication between the processor and an external agent. sysadc[3:0] input/output system address/data check bus a 4-bit bus containing parity check bits for the sysad bus during data cycles. syscmd[8:0] input/output system command/data identifier bus a 9-bit bus for command and data identifier transmission between the processor and an external agent. syscmdp input/output reserved for system command/data identifier bus parity for the rm5231, unused on input and zero on output.
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 27 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released table 6 clock/control interface table 7 interrupt interface table 8 jtag interface pin name type description sysclock input system clock master clock input used as the system interface reference clock. all output timings are relative to this input clock. pipeline operation frequency is derived by multiplying this clock up by the factor selected during boot initialization. vccp input quiet vcc for pll quiet vcc for the internal phase locked loop. must be connected to vccint through a filter circuit. vssp input quiet vss for pll quiet vss for the internal phase locked loop. must be connected to vss through a filter circuit. pin name type description int[5:0]* input interrupt six general processor interrupts, bit-wise ored with bits 5:0 of the interrupt register. nmi* input non-maskable interrupt non-maskable interrupt, ored with bit 6 of the interrupt register. pin name type description jtdi input jtag data in jtag serial data in. jtck input jtag clock input jtag serial clock input. jtdo output jtag data out jtag serial data out. jtms input jtag command jtag command signal, signals that the incoming serial data is command data.
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 28 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released table 9 initialization interface table 10 power supply note 1. an "*" at the end of the signal name denotes active low. pin name type description bigendian input allows the system to change the processor addressing mode without rewriting the mode rom. vccok input vcc is ok when asserted, this signal indicates to the rm5231 that the 3.3v power supply has been above 3.0v for more than 100 milliseconds and will remain stable. the assertion of vccok initiates the reading of the boot-time mode control serial stream. coldreset* input cold reset this signal must be asserted for a power on reset or a cold reset. coldreset must be de-asserted synchronously with sysclock. reset* input reset this signal must be asserted for any reset sequence. it may be asserted synchronously or asynchronously for a cold reset, or synchronously to initiate a warm reset. reset must be de-asserted synchronously with sysclock. modeclock output boot mode clock serial boot-mode data clock output at the system clock frequency divided by 256. modein input boot mode data in serial boot-mode data input. pin name type description vccint input power supply for core. vccio input power supply for i/o. vss input ground return.
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 29 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released 5 absolute maximum ratings 1 symbol rating limits unit v term terminal voltage with respect to gnd ? 0.5 2 to +3.9 v t case operating temperature commercial 0 to +85 c industrial ? 45 to +85 c t stg storage temperature ? 55 to +125 c i in dc input current 20 3 ma i out dc output current 20 4 ma notes 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v in minimum = -2.0 v for pulse width less than 15 ns. v in should not exceed 3.9 v. 3. when v in < 0v or v in > vccio. 4. not more than one output should be shorted at a time. duration of the short should not exceed 30 seconds.
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 30 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released 6 recommended operating conditions notes 1. vccio should not exceed vccint by greater than 1.2 v during the power-up sequence. 2. applying a logic high state to any i/o pin before vccint becomes stable is not recommended. 3. as specified in ieee 1149.1 (jtag), the jtms pin must be held high during reset to avoid entering jtag test mode. 4. vccp must be connected to vccint through a passive filter circuit. see the rm5200 user ? s manual for the recommended filter circuit. grade temperature vss vccint vccio vccp commercial 0 c to +85 c (case) 0 v 2.5 v 5% 3.15 v ? 3.45 v 2.5 v 5% industrial -40 c to +85 c (case) 0 v 2.5 v 5% 3.15 v ? 3.45 v 2.5 v 5%
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 31 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released 7 dc electrical characteristics parameter minimum maximum conditions v ol 0.2 v |i out |= 100 a v oh vccio - 0.2 v v ol 0.4 v |i out | = 2 ma v oh 2.4 v v il -0.3 v 0.8 v v ih 2.0 v vccio + 0.3 v i in 1 5 a 1 5 a v in = 0 v in = vccio
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 32 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released 8 power consumption parameter conditions: max: vccint = 2.625 typ: vccint = 2.5 v cpu speed 150 mhz 200 mhz 250 mhz typ 1 max 2 typ 1 max 2 typ 1 max 2 vccint power (mwatts) standby 200 250 350 active r4000 write protocol with no fpu operation (integer instructions only) 1100 2200 1425 2800 1725 3450 write re-issue or pipelined writes with superscalar 1225 2450 1600 3200 1900 3800 notes 1. typical integer instruction mix with nominal supply voltage (untested). 2. worst case instruction mix with maximum supply voltage. 3. i/o supply power is application dependant, but typically <20% of vccint.
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 33 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released 9 ac electrical characteristics 9.1 capacitive load deration 9.2 clock parameters parameter symbol cpu speed units 150 ? 250 mhz min max load derate c ld 2ns/25 pf io power derate 17.5 mw/25 pf/ mhz io power derate @ 20 pf load 4.0 5.5 mw/ mhz parameter symbol test conditions cpu speed units 150 mhz 200 mhz 250 mhz min max min max min max sysclock high t sch transition 5 ns333ns sysclock low t scl transition 5 ns333ns sysclock frequency 25 75 25 100 25 100 mhz sysclock period t scp 40 40 40 ns clock jitter for sysclock t ji 200 200 150 ps sysclock rise time t cr 222ns sysclock fall time t cf 222ns modeclock period t modeckp 256 256 256 t scp jtag clock period t jtagckp 444t scp note 1. operation of the rm5231 is only guaranteed with the phase lock loop enabled.
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 34 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released 9.3 system interface parameters 1 9.4 boot-time interface parameters parameter symbol conditions 150 ? 250 mhz cpu speed min max units data output 2,3 t do mode14..13 = 10 (fastest) 5 1.0 4.5 ns mode14..13 = 11 5 1.0 5.0 ns mode14..13 = 00 5 1.0 5.5 ns mode14..13 = 01 (slowest) 5 1.0 6.0 ns data setup 4 t ds t rise = see above table t fall = see above table 2.5 ns data hold 4 t dh 1.0 ns notes 1. timings are measured from 1.5 v of the clock to 1.5 v of the signal. 2. capacitive load for all maximum output timings is 50 pf. minimum output timings are for a theoretical no load condition - untested. 3. data output timing applies to all signal pins whether tristate i/o or output only. 4. setup and hold parameters apply to all signal pins whether tristate i/o or input only. 5. only mode 14:13 = 00 is tested and guaranteed. parameter symbol cpu speed units 150 ? 250 mhz min max mode data setup t ds (m) 4 sysclock cycles mode data hold t dh (m) 0 sysclock cycles
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 35 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released 10 timing diagrams figure 9 clock timing 10.1 system interface timing (sysad, syscmd, validin*, validout*, etc.) figure 10 input timing figure 11 output timing sysclock t rise t fall t high t low t jitterin t ds t dh data sysclock data t do min t do max sysclock data data data
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 36 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released 11 packaging information bottom view odd lead sides (b) x 3 x = a, b, or d even lead sides e/2 detail ? a ? x 3 x = a, b, or d gage plane 0.25 0-7 1.60 ref. l c c 0.13/0.30 r detail ? b ? a1 13 a2 2 h 0.40 min. 0.13 r. min. section c-c with lead finish base metal 0.13/0.19 11 0.13/0.23 8 b b 1 seating plane c a see detail ? b ? 12-16 e b (n-4)x d a-b c 8 top view 4.00 r. 4 places b 3 11.0 ref. 0.20 c a-b d 4x 11.0 ref. see detail ? a ? 4 d d/2 a 3 2.00 dia 4 places e/2 d 3 e 4 75 da-b h 0.20 4x 0.10 11 11 11 0.076 c d1/2 d1 5 7 (d2) 11.0 ref. (e2) ? country of origin ? mark 3.00 ref. dia. 4 places e1/2 e1 11.0 ref. 0 min. hx hy 10 a,a,a m all dimensions are in millimeters unless otherwise noted. 1 128 pin #1 i.d. symbol min nominal max note a ? 3.70 4.07 a1 0.25 0.33 ? a2 3.17 3.37 3.67 d 31.20 bsc to be determined at seating plane c. d1 28.00 bsc dimensions d1 and e1 do not include mold protrusion. allowable mold protrusion is 0.254 mm per side. dimension d1 and e1 do include mold mismatch and are determined at datum plane h. d2 24.00 ref. e 31.20 bsc to be determined at seating plane c. e1 28.00 bsc dimensions d1 and e1 do not include mold protrusion. allowable mold protrusion is 0.254 mm per side. dimension d1 and e1 do include mold mismatch and are determined at datum plane h. e2 24.00 ref. d3 21.0 ref. e3 21.0 ref. l 0.65 0.70 0.95 e 0.80 bsc b0.30 ? 0.45
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 37 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released notes b1 0.30 0.35 0.40 a,a,a 0.16 thetaja 13.7 c/w thetajc 1.5 c/w symbol min nominal max note 1. all dimensioning and tolerances confirm to asme y14.5 ? 1994. 2. datum plane h located at the bottom of the mold parting line and coincident with where lead exits plastic body. 3. datums a ? b and d to be determined where center line between leads exits plastic body at datum plane h. 4. to be determined at seating plane c. 5. dimensions d1 and e1 do not include mold protrusion. allowable mold protrusion is 0.254 mm per side. dimension d1 and e1 do include mold mismatch and are determined at datum plane h. 6. ? n ? is number of terminals. 7. package top dimensions are smaller than bottom dimensions by 0.20 millimeters and top of package will not overhang bottom of package. 8. dimensions b does not include damabr protrusion. allowable damabr protrusion shall be 0.08 mm. total in excess of b dimension at maximum material condition. damabr can not be located on the lower radius or the foot. the dimension space between protrusion and an adjacent lead shall not be less than 0.07 mm for 0.4 mm and 0.50 mm pitch package. 9. all dimensions are in millimeters. 10. the optional exposed heat shrink is coincident with the top or bottom side of the package and not allowed to protrude beyond that surface. 11. these dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 12. this drawing conforms to jedec registered outline ms-022. but the heat slug dimension was not specified on jedec. 13. a1 is defined as the distance from the seating plane to the lowest point of the package body.
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 38 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released 12 rm5231 128 pqfp package pinout pin function pin function pin function pin function 1 nc 33modein 65nmi* 97nc 2 nc 34 rdrdy* 66 extrqst* 98 nc 3 vccio 35 wrrdy* 67 reset* 99 nc 4 vss 36 validin* 68 coldreset* 100 nc 5 sysad4 37 validout* 69 vccok 101 vccio 6 sysad5 38 release* 70 bigendian 102 vss 7 vccint 39 vccp 71 vccio 103 sysad28 8 vss 40 vssp 72 vss 104 sysad29 9 sysad6 41 sysclock 73 sysad16 105 vccint 10 sysad7 42 vccint 74 vccint 106 vss 11 sysad8 43 vss 75 vss 107 sysad30 12 sysad9 44 syscmd0 76 sysad17 108 sysad31 13 vccio 45 syscmd1 77 sysad18 109 sysadc2 14 vss 46 syscmd2 78 sysad19 110 vccint 15 sysad10 47 syscmd3 79 vccint 111 vss 16 sysad11 48 vccio 80 vss 112 sysadc3 17 vccint 49 vss 81 sysad20 113 vccio 18 vss 50 syscmd4 82 sysad21 114 vss 19 sysad12 51 syscmd5 83 vccio 115 sysadc0 20 sysad13 52 vss 84 vss 116 sysadc1 21 sysad14 53 syscmd6 85 sysad22 117 sysad0 22 vccint 54 syscmd7 86 sysad23 118 sysad1 23 vss 55 syscmd8 87 sysad24 119 vccint 24 sysad15 56 syscmdp 88 sysad25 120 vss 25 vccio 57 vccint 89 vccint 121 sysad2 26 vss 58 vss 90 vss 122 sysad3 27 modeclock 59 int0* 91 sysad26 123 vccio 28 jtdo 60 int1* 92 sysad27 124 vss 29 jtdi 61 int2* 93 vccio 125 nc 30 jtck 62 int3* 94 vss 126 nc 31 jtms 63 int4* 95 nc 127 nc 32 vccio 64 int5* 96 nc 128 nc
proprietary and confidential to pmc-sierra, inc and for its customer ? s internal use 39 document id: pmc-2002165, issue 1 rm5231 ? microprocessor with 32-bit system bus data sheet released 13 ordering information valid combinations rm5231 ? 150 ? q rm5231 ? 200 ? q rm5231 ? 250 ? q rm5231 ? 200 ? qi (contact sales prior to design) rm5231 -123 a i temperature grade: (blank) = commercial i = industrial package type: q = power quad 4 (pq-4) device maximum speed device type

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